1. Field of the Invention
The present invention relates to low thermal budget gated resistor structures, and more particularly, its application for device level three-dimensional (3D) integration with higher interconnect density compared to the current wafer bonding/packaging and “through silicon via” (TSV) technology.
2. Description of the Related Art
In response to the increasing challenges in maintaining technology advancements through traditional “constant electrical field” scaling at a pace consistent with Moore's law, alternative methods to achieve enhanced system level performance are becoming increasingly important. Three-dimensional (3D) integration technology, which means having at least two active device layers connected vertically, has the potential to provide significant performance enhancements by reducing long lateral signal connection path into short vertical one while at the same time increasing the device density.
Overall, 3D integration technology can be broadly defined as any technology that stacks semiconductor elements, such as electrical transistors or optical devices, on top of each other and uses both vertical and lateral interconnects to transfer signals through different layers of semiconductor elements. Currently, there are two major approaches to achieve wafer level 3D integration: wafer bonding and monolithic stacking.
Wafer bonding allows individual layers to be fabricated separately with the existing fabrication technology and then these layers are bonded to each other after devices have already been formed. It requires relative small modification of device fabrication technology but requires additional process development to reliably thin the wafer, attach wafers with high alignment accuracy, and to form high quality interconnects with high aspect ratio. Usually, the pads and interconnects in this approach have to be large enough to account for misalignment during the wafer bonding process. The most commonly used method to form such vertical connections is by using through-silicon via (TSV) either before or after the devices have been fabricated. The dimension of TSV is limited by the ability of high aspect ratio etching and the alignment accuracy during bonding. Typically the smallest dimension of TSV is around 0.5 um to 1 um. Such dimension is small enough for most applications but still too big if compared to the capability of device level interconnects/via, which can be smaller than 0.1 um.
By contrast, monolithic stacking refers to processing each layer directly on top of lower layers and it generally provides higher interconnect density because each layer is aligned precisely to the lower existing layer using advanced lithography tool and interconnect dimension as small as 0.1 um can be achieved. However, monolithic stacking involves significant processing modifications for the layer that fabricated on top of the existing layer. In general, the process temperature for the upper layer must be kept lower than those used for the lower layer to avoid further dopant diffusion and junction deformation. If there are metal layers in the structure, temperatures must be kept below 450° C. to avoid metal deformations. Such thermal constrains poses significant limitation on the feasibility of monolithic stacking.
Basically, the core difference between these two methods simply represents the trade-off between performance (high interconnect density) and fabrication complexity (thermal constraints). FIG. 1 shows the general process flow of wafer bonding and monolithic stacking. Currently, wafer bonding using TSV as the vertical interconnect requires less thermal budget and can be adapted easily by current technology. As a result, most of the focus of industry is now on TSV/wafer bonding technology combined with advanced packaging techniques. For monolithic stacking, despite its potential ability of providing high interconnect density, the difficulty in fabrication, particularly thermal budget, limits its adoption.
To further explain such difficulty of thermal constrains, a brief illustration of current CMOS process is provided. FIG. 2 schematically depicts a sectional view of CMOS transistor, where the bottom dashed box indicates the front-end-of-line (FEOL) process, and the top dashed box indicates back-end-of-line (BEOL) process. More particularly, the FEOL denotes the first portion of IC fabrication where the individual devices are patterned in the semiconductor. In the shown example of FIG. 2, FEOL contains all processes of CMOS fabrication needed to form fully isolated CMOS elements such as gate module, source and drain module. The BEOL denotes the second portion of IC fabrication where the individual devices get interconnected with wiring on the wafer. In the shown example of FIG. 2, BEOL contains the metal plug and interconnect atop the gate, source and drain of the CMOS transistors.
In modern VLSI technology, most process steps such as lithography, deposition and etching, are relatively low temperature or can be done at low temperature. There are, however, two high temperature critical steps limit the feasibility of monolithic stacking integration: getting a high quality single crystal substrate on top of existing layer/devices, and subsequent dopant activation. The activation of source/drain (S/D) in current Si technology often requires temperature much higher than 450° C., and low temperature source/drain annealing results in significant performance loss and high contact resistance. Laser annealing has been pursued because the energy can be limited locally, but such process generally has lower throughput. Aside from dopant activation, getting a single crystal substrate to start with is also problematic because it is hard to form single crystal layer on top of the amorphous isolation layer, which encapsulates the devices in the lower layer. Even with long time and high temperature anneal, the starting layer could still be poly-grained instead of single crystal. These two constrains can be seen also in FIG. 1, which shows that to achieve high performance by monolithic stacking, these two thermal bottlenecks: getting a single crystal substrate in which to build high performance devices in the upper layers and the subsequent dopant activation for forming p-n junctions have to be resolved.
Up to now, one has to wonder if there is a desirable process methodology for building multiple layer devices with both acceptable thermal budget and high interconnect density. As a result, a “bonding substrate/monolithic contact” (BSMC) approach is proposed to combine both advantages from wafer bonding and monolithic stacking.
Considering these two high temperature bottlenecks from a 3D integration point of view, first, getting single crystal film as an upper layer does not require any precise alignment to a lower layer because at this stage most fine pitch device modules, such as gate module or source/drain module, are not fabricated yet. Hence it is possible to take advantage of the wafer bonding technique by attaching a single crystal layer to the acceptor wafer instead of monolithically growing a single crystal upper layer. Bonding a single crystal layer prepared with standard higher temperature process can avoid significant thermal impact to the lower layers with almost no alignment penalty and performance loss because at this stage the bonded single crystal are still close to blank film without any fine pitch module done. This wafer bonding is different from the previous mentioned one while the previous one refers to bonding two already processed wafers containing multiple transistors and semiconductor elements. However, source/drain regions activation is more problematic since traditionally they are done after fine pitch gate patterning. As a result, if the fine pitch gate module and S/D anneal are done before bonding, then the whole approach actually becomes the previous mentioned wafer bonding technique which still suffers from the possibility of misalignment during bonding. So the S/D formation still needs to be done after bonding a single crystal layer in order to maintain the advantages of high interconnect density.
Based on the process characteristics described above, the “bonding substrate/monolithic contact” (BSMC) approach can be further illustrated in FIG. 3. The concept is to form single crystal film or layer on a donor wafer using standard high temperature processes and then bond the layer to another acceptor wafer. The subsequent device fabrication, including gate, S/D and via/contact formations can then be processed with accurate alignment to the lower layers on the acceptor wafer. Moreover, in order to solve the S/D annealing issue after bonding, as illustrated in FIG. 3, there are several options including: low temperature S/D activation, Laser S/D activation, Schottky barrier S/D, and several gated resistor structures which are part of this invention and will be described below. Moreover, in this invention, a novel recessed channel gated resistor structure, which requires no high temperature S/D activation after gate patterning, is proposed to replace the conventional lateral “npn or pnp” transistor structure. This invention hence provides a novel way for achieving high performance 3D integration.